Power semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) are commonly used as power devices in applications, such as automotive electronics, power supplies, telecommunications, which applications require devices to operate at currents in the range of tens up to hundreds of amperes (A).
The IGBT combines the simple gate-drive characteristics of MOSFET devices with the high-current gain and low-saturation-voltage capability of bipolar transistors by combining an insulated-gate FET for the control input and a bipolar power transistor as a switch in a single device.
A typical simplified structure of a cell of a planar IGBT is shown in FIG. 1. As is well known, the active area of an IGBT device comprises a plurality of such cells. The IGBT cell comprises an anode electrode 2 electrically connected to a p+ type anode layer 4. A n type semiconductor layer 5 is formed over the p+ type anode layer 4. A n− type base semiconductor layer 6 is formed over the n type semiconductor layer 5 and p type body regions 8 are formed in the n− base semiconductor layer 6. N+ type emitter regions 10 are formed in the p type body regions 8 and a polysilicon layer region 12 acting as a gate electrode is formed over portions of the n− type base semiconductor layer 6, the p type body regions 8 and the n+ type emitter regions 10. A cathode electrode 14 is electrically shorted to the p type body regions 8 and the n+ type emitter regions 10. By applying a voltage to the gate electrode and so across the gate oxide dielectric layer 13, the IGBT device is turned on and a channel will be formed at the surface of the p type body regions 8, between the n+ emitter region 10 and the n− type base semiconductor layer 6, under the insulated gate electrode 12 connecting the n+ type emitter regions and the p+ type anode layer allowing a current to flow between the anode and the cathode electrodes.
Trench-gate IGBTs have also been developed in which the insulated gate electrodes are formed in trenches extending into the n− type base semiconductor layer and intersecting the n+ type emitter regions.
A disadvantage of IGBTs over a standard MOSFET transistor is the IGBTs slower turn-off time. Faster turn-off times can be achieved by certain changes in design or processes, but at the expense of higher saturated voltage drops between anode and cathode electrodes (Vcesat). Devices with higher Vcesat have smaller Safe Operating Areas (SOA) of operation which is generally not desirable.
Decreasing Vcesat also allows the on-state losses to be reduced, and the die size decreased, which enables the size of the full operating system to be reduced. Also, the thermal behaviour is enhanced by decreasing Vcesat. Usually, Vcesat can be improved by increasing the MOSFET transconductance (which is the upper part of the IGBT device). Unfortunately, during a short-circuit event, there is nothing to limit the amount of current (Icsat) passing through the device, except reducing its transconductance which in turn will degrade the Vcesat.
In order to improve performance of IGBTs, methods have been developed to reduce Vcesat. However, as Vcesat is reduced, the current in the anode electrode at saturation Icsat is increased. This reduces the short circuit capability of the device. Thus, there is a trade-off between Vcesat and Icsat which needs to be accounted for when attempting to reduce Vcesat.
An article entitled ‘A Planar-Gate High-Conductivity IGBT (HiGT) With Hole-Barrier Layer’ by Mutsuhiro Mori, Kazuhiro Oyama, Taiga Arai, Junichi Sakano, Yoshitaka Nishimura, Koutarou Masuda, Katsuaki Saito, Yoshihiro Uchino and Hideo Homma, in IEEE Transactions on Electron Devices, Vol. 54, No. 6, June 2007, ages 1515 to 1520 describes a planar IGBT with a double diffused MOS structure and a n type hole barrier layer surrounding a p type base region. The hole barrier layer prevents the holes from flowing into the p type base region and stores them in the n type hole barrier layer. The planar structure having the hole barrier layer described in this article reduces Vcesat, regardless of the injection efficiency of the p type anode layer, while it maintains a high breakdown voltage by controlling the sheet carrier concentration of the hole barrier layer and maintains Icsat at a level that is similar to that of conventional IGBTs. The hole barrier layer is formed around the p type base region by implantation. However, the diffusivity of n type dopants is very low compared to p type dopants so manufacturing the structure described in this article in practice would be difficult to achieve, particularly since it would be hard to autoalign the n type hole barrier layer and the p type base region. In addition, a special mask must be used to form the hole barrier layer, which mask has to be autoaligned with the base region in order to prevent detrimental breakdown voltage and threshold voltage variations. Thus, the method disclosed in this article requires additional critical manufacturing steps which add to the cost of manufacturing the device.
US patent application no. 2005/0263853 describes a trench-gate IGBT having a carrier stored layer formed under a p type base region and having a doping or impurity concentration that is greater than the doping concentration of the n− type base semiconductor layer. Since the carrier stored layer is formed under the p type base region, the holes from the p+ anode layer are prevented from passing to the cathode electrode and the holes are stored in the carrier stored layer. This results in a reduction in the Vcesat voltage. However, the presence of the carrier stored layer increases the variation of the threshold voltage. This variation is detrimental to the control of the current distribution through the gate electrode over the die. This patent application also describes embodiments in which the doping concentration in the carrier stored layer is less in regions of the carrier stored layer adjacent the trenches compared to regions of the carrier stored layer other than adjacent the trenches so as to control the gate capacity and short circuit current and to prevent variations in threshold voltage. The different regions of the carrier stored layer having different doping concentrations is achieved by, for example, varying the thickness of the carrier stored layer, with the thinner regions having a lower doping concentration. The carrier stored layer is formed by selective implantation using a specific mask. The mask has to be autoaligned with the trenches in order to prevent a too highly doped channel region being formed. Thus, the method disclosed in this application requires additional critical manufacturing steps which add to the cost of manufacturing the device.